Because of the quick advancement of semiconductors equipment and the rising require for batterypowered moveable gadgets, designers have scaled down feature sizes, resulting in lower The integration of exceedingly complicated functionalities on a single chip, as well as the threshold voltage. Chip's maximum power method is used in both technological and execution aspects. To expand the number of devices in a concert, three critical characteristics are required: system speed, small footprint, and low power usage. The total power utilization of integrated devices is resolute by leakage current dissipation in particular. The CMOS VLSI Technology's leakage power is a major issue. A Leakage Power Minimization the Technique is used in the research to decrease outflow Power in CMOS devices. Currents of leakage are tracked and compared. The Charge is initiated by the Comparator. Pumping blood to the body (V body). These circuits have been modeled. This was accomplished with the help of TSMC 0.35m technology and diverse operational conditions. The current steered digital-to-analog converter is known as CSDAC (Steering Digital-to-Analog Converter). As a proof of concept, it's being used as a test core. Core of the test (eg.8-bit CSDAC).It consumed 347.63 mill watts of power. The LPMT circuit alone uses a significant amount of energy.6.3405 mW in power Leakage is reduced when this technique is used.