Manuscript Title:

FPGA IMPLEMENTATION OF ENHANCED THROUGHPUT DESIGN OF AES ARCHITECTURE USING NIKHILAM SUTRA

Author:

BINDU SWETHA PASULURI, Dr. V. J. K. KISHOR SONTI

DOI Number:

DOI:10.17605/OSF.IO/5MEJW

Published : 2022-06-23

About the author(s)

1. BINDU SWETHA PASULURI
2. Dr. V. J. K. KISHOR SONTI

Full Text : PDF

Abstract

The exponential growth of the internet and contemporary communications users have established safety as a fundamental design feature for encrypted transmission. The Enhanced Cryptography Standard is perhaps the most widely used cryptography information security algorithm standard that has been authorized by NIST. This paper proposes a high-throughput design for the AES Algorithm with huge key sizes. AES would be a block cipher that ensures data security by using key lengths of 128,192 and 256- bits. The design concept focuses on a 256-bit key size classification algorithm since a big key size is required to ensure excellent security. Additionally, simultaneous key expansion & encryption/decryption processes would be pipelined to maximize speed. Parallelization of a key expansion module's subprocesses would be used to reduce the critical chain latency. The S-box comprising sub-byte & inverse sub-byte operations has been developed with compound field arithmetic operations to reduce time and area further. The work Increased throughput by 50%, area reduced by 34.32 %, and latency by 20% compared to the old approach with modified nikhilam sutra. Additionally, integrated AES encryption/decryption is planned and implemented on the FPGA Zed board utilizing Verilog HDL in Xilinx Vivado.


Keywords

Advanced encryption standard, throughput, FPGA, high security, nikhilam sutra.