1. ASHA CN - Dept. of Electronics and Communication Engineering, Acharya Institute of Technology, Bangalore.
2. JAYALAXMI H - Dept. of Electronics and Communication Engineering, Acharya Institute of Technology, Bangalore.
3. SAPNA KUMARI C - Dept. of Electronics and Communication Engineering, Nitte Meenakshi Institute of Technology, Bangalore.
4. NAGAPUSHPHA KP - Dept. of Electronics and Communication Engineering, Acharya Institute of Technology, Bangalore.
Addition is one of the most vital and initial operations among all arithmetic operations and is utilized in many of the mathematical equations. In digital world, the addition operation can be performed by several adders. These adders produce carries with preferred power and delay. One of the most basic functional units for performing modular arithmetic in different cryptography and PRBG (pseudorandom bit generator) algorithms is Three-operand binary adder. Because of ripple-carry stage, the Carry save three-operand Adder (CS3A) has long propagation delay. In addition, a parallel prefix two-operand adder (PP2A) like HCA (Han-Carlson) is used in the addition of three-operands. Hence new higher speed and less power adder architecture is presented in this paper using the pre-computing bitwise addition follow by carry-prefix computation logic for performing binary addition of three operands that can consume less power and low area and adder delay is drastically reduced to O(log2 n). The ISE Xilinx 14.7 software is used for simulation and synthesizing these processes. The simulation results of presented adder will represent that it will have less power dissipation, lesser area and less delay compared to CS3A adder. More over the presented adder will achieve least PDP (power-delay-product) and ADP(area-delay-product) than previous threeoperand adder methods
Carry Save Adder (CSA), Three-operand binary adder, VLSI architecture, Han-Carlson adder (HCA), low power, and high speed.