1. MANJUNATH PATIL - Ramaiah Institute of Technology, Department of Electronics and Communication Engineering, Bengaluru,
2. M. NAGABUSHANAM - Ramaiah Institute of Technology, Department of Electronics and Communication Engineering, Bengaluru, India.
3. M. C. PARAMESHWARA - Vemana Institute of Technology, Department of Electronics and Communication Engineering, Bengaluru, India.
: As the use of digital systems grows, so does the demand for converting analog data to digital data. Because of its moderate conversion speeds, good resolution, and small die area, Successive Approximation Register (SAR) Analog to Digital Converters (ADC) are commonly used. Data converters are essential for converting analog signals to digital signals. Due to its good balance of power, area, and speed considerations, SAR ADC is the most recommended architecture for ADC implementation. A unique high gain operational amplifier is presented as a comparator for a 10-bit SAR-ADC in the presented work. This work implements the 10-bit SAR-ADC with a D flip-flop (Delay flip-flop) based SAR logic, a high gain operational amplifier as a comparator, and a Report to Report (R2R) Digital to Analog data-converter (DAC). The work is implemented in Cadence Exploratory Data Analysis (EDA) utilizing the gpdk090 library in 90 nm CMOS (Complementary Metal-OxideSemiconductor) technology. The Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) are determined to be less than 1LSB (Least Significant Bit) on average. With a sample rate of 150 MS/s and a supply voltage of 1 V, the ADC consumes 265.8 µW of power with Effective Number of Bits (ENOB) of 9.39 bits and Signal Difference to Noise Ratio (SNDR) of 58.2dB. The SAR ADC that has been presented uses less power and can be used in portable devices.
Digital to analog converter (DAC), Successive approximation register (SAR), SAR logic, Sample and hold circuit, comparator.