As semiconductor technology has evolved, the convergence of a large series of processing cores on a single silicon chip known as a System on Chip (SoC) [1] has expanded substantially. With the increase in the applications for modern technology, the amount of computational power that can be handled on a single chip has greatly expanded. The Network on Chip (NoC) has successfully replaced the traditional bus-based mode of transportation in order to satisfy the SoC connectivity standards. NoC is an on-chip communication strategy aimed at reconciling inter-core and system messages in tandem. The NoCs are also scalable since, it overcomes network congestion, area utilization and operates at higher frequencies. Congestion is also a critical part of any wireless networks against packet loss and latency. This motivated us to design and implement a FPGA based router architecture for Network on Chip. The goal of this research paper is to efficiently propagate data packets to their intended destination and thereby, the network parameters such as area and transmission rate are considered to improve the performance of the network.